The use of DC-DC power converters is becoming increasing widespread in electrical products, such as portable computers and mobile devices. In many cases, the performance of the product depends on the efficiency of the power converter. Because of this dependency, product manufacturers are demanding more efficient converters, for example, to preserve battery life or improve another performance aspect.
Generally, two types of general schemes may be used for DC-DC converters, namely, non-synchronous and synchronous converters.
FIG. 1 shows a simplified schematic diagram for a non-synchronous buck converter 100. The illustrated converter 100 includes a FET 102 (labelled as Q1), such as a MOSFET, a diode 104 (typically a Schottky diode), an inductor 106 (L), a capacitor 108 (C) and a load 110 (R). The FET 102 and the diode 104 act as switches with the FET 102 receiving a pulse width modulated (PWM) gate signal 112. The PWM signal 112 is controlled to turn the FET 102 “on” and “off” to regulate the output voltage (Vout). When the FET 102 is turned on the Schottky diode 104 is reversed biased. In this configuration energy is delivered from an input voltage source to the inductor 106 and the load 110. On the other hand, when the FET 102 is turned off, energy stored in the inductor 106 is discharged and the resultant inductor current I(L) is conducted via the Schottky diode 104, which is forward biased. In operation, the output voltage (Vout) of the illustrated converter 100 is maintained by controlling the duty cycle of the PWM signal 112 to provide a wider pulse signal to the FET 102 when the output voltage (Vout) is less than a reference voltage (Vref), or providing a narrower pulse signal to the FET 102 when the output voltage (Vout) exceeds the reference voltage (Vref). In this respect, in the example shown in FIG. 1, providing a wider pulse signal to the FET 102 increases the energy delivered to the load 110 from the inductor (L) 106, and thus increases the output voltage (Vout), whereas providing a narrower pulse signal to the FET 102 reduces the energy delivered to the load 110 from the inductor 106, and thus reduces the output voltage (Vout). The capacitor 108 is provided to decrease output voltage ripple.
Non-synchronous converters provide relatively efficient operation when the load demands a relatively high current and high output voltage (Vout). However, when the load (R) demands no or low current, a non-synchronous converter may operate in a low voltage condition or mode. In this condition, the forward voltage drop of the diode 104, which is typically not less than 0.3V, will reduce the efficiency of the converter, particularly at low output voltages as the relative proportion of the forward voltage drop across the diode increases compared to the output voltage (Vout).
In a synchronous converter the diode is replaced by a FET, such as a MOSFET to provide a synchronous rectifier (SR) having a low “on” resistance (RDSON). When a MOSFET is turned on it thus provides a voltage drop which is less than that of the diode at a given current. Furthermore, the “on” resistance (RDSON) of FETs can be lowered, either by increasing the size of the die or by paralleling discrete devices. Consequently, a MOSFET used in place of a diode may provide a significantly smaller voltage drop at a given current compared to a diode. This reduced voltage drop may improve the efficiency of synchronous rectification, which may be beneficial in applications sensitive to efficiency, converter size, and thermal performance, such as portable or handheld devices. Furthermore, since MOSFET manufacturers are constantly introducing new MOSFET technologies that have lower RDSON and total gate charge (QG), further efficiency improvements may be possible which may make it easier to implement synchronous rectification in power converter design and lead to further efficiency improvements.
FIG. 2A depicts, for illustrative purposes, a simplified schematic diagram for a synchronous “buck” converter 200 for converting an input voltage (Vin) to a lower output voltage (Vout). In this example, the FET 202 (Q1) is turned on for a sufficient duration to energise the inductor 204 (L1) to meet the current demand by the load 206 (R). The FET 208 (Q2) replaces the diode 104 depicted in FIG. 1. In this example, the FET 208 provides a synchronous rectifier which provides a switched conduction path which is controlled by, and thus depends on, a second gate signal (labelled as ‘Q2 Gate Signal’). In operation, the inductor current I(L) increases linearly when Q1 is turned on (and Q2 is switched off) and decreases linearly when Q1 is switched off (and Q2 is switched on).
A synchronous converter such as of the type depicted in FIG. 2A may operate in one of two modes, namely, a continuous current mode (CCM) or a discontinuous current mode (DCM). In relation to the converter 200 shown in FIG. 2A, in continuous current mode when Q1 is turned off the inductor current I(L) does not decrease to zero, but instead continues to flow in one direction at all times. On the other hand, in discontinuous current mode, which may occur during low load current demand, the inductor current I(L) is interrupted and indeed may be become negative at some point, thus contributing to a reduction in conversion efficiency.
FIG. 2B shows a signal timing diagram illustrating the timing relationship between the Q1 gate signal (labelled as “Q1 gate signal”), the Q2 gate signal (labelled as “Q2 gate signal”) and the inductor current I(L) during operation of the converter shown in FIG. 2 in discontinuous current mode. As shown in FIG. 2B, when operating in DCM it is possible for the inductor current I(L) to reverse direction, and thus become negative (region shown shaded), if the Q2 gate signal maintains FET Q2 in the on state after the inductor (L) has discharged the energy stored by the inductor (L) when the Q1 gate signal held Q1 on.
In view of the above, a problem which may arise during operation of a synchronous converter as compared to operation of non-synchronous converter are losses in efficiency which may arise due to the synchronous rectifier (i.e. Q2) permitting negative inductor current. Ideally, the synchronous rectifier should be capable of emulating the diode in the non-synchronous converter and inhibit the current exactly at the “zero current point” to thereby prevent negative current through the inductor.
One prior art approach for mitigating the negative current problem which may occur during discontinuous current mode involves detecting the inductor current and inhibiting or shutting off the gate signal to the synchronous rectifier when the polarity of the inductor current I(L) changes. However, such an approach may require additional sensing elements which could themselves introduce undesirable signal noise and additional efficiency losses.
Another approach for improving the operation of a synchronous rectifier during discontinuous current mode is described in US 2009/0323375. One approach described in US 2009/0323375 attempts to regulate a synchronous rectifier by monitoring the average duty cycle of the PWM control signal to determine the effect of varying a reference voltage (Vref) on the duty cycle to establish when a minimum duty cycle condition exists for the PWM control signal. This approach thus involves a trial and error process which relies on the load remaining unchanged for the duration of the regulation. However, if the load changes suddenly, the regulation may need to be reset or restarted from an unknown, and therefore not optimal, point.
It would be desirable to provide an efficient and low loss circuit and method for controlling a synchronous rectifier.
The discussion of the background to the invention herein is included to explain the context of the invention. This is not to be taken as an admission that any of the material referred to was published, known or part of the common general knowledge as at the priority date of any of the claims.